Flash memory devices are a type of nonvolatile semiconductor memory device. Flash memory devices are regarded as being highly adaptable to large storage capacities and high-frequency operation in applications requiring large-capacity storage devices and coded memories for mobile apparatuses. Flash memory devices are generally classified into BAND and NOR types by the logical pattern of the cell array. The memory cell array of the NOR-type flash memory device is structured such that a plurality of memory cells are arranged as being connected to a single bit line in parallel. In contrast, the BAND-type flash memory device has a memory cell array in which a plurality of memory cells are connected in series from a single bit line. The NOR-type flash memory devices are widely used in applications requiring high-frequency operations because they are operable with high speed in programming and reading operations, relative to the BAND-type flash memory devices. Data values within the flash memory device are defined by the threshold voltages of the memory cells, in which programming operations are carried out by changing the cell threshold voltages. It is now conventional to regulate the cell threshold voltages by the ISPP scheme during programming operations.
FIG. 1 illustrates the pulses of programming and verifying voltages applied to a wordline of a memory cell during a programming operation with the ISPP scheme in a general flash memory. As shown in FIG. 1, in a typical cycle of the ISPP scheme, a unit step of incrementing a program voltage is confined to a ΔV value and a unit verifying time is fixed to Δt. Such fixed ranges for the program voltage step and the unit verifying time are contrary to achieving narrow distribution profiles of cell threshold voltages in multi-level cell (MLC) arrangements. In detail, the fixed range of the incremental program voltage step raises the probability of shifting cell threshold-voltage distribution profiles upward from a verifying voltage Vveri, after the programming operation for those memory cells that have threshold voltages near to the verifying voltage Vveri. This effect arises when the incremental step of the program voltage is excessively high to inject the appropriate amount of hot electrons into a floating gate. The threshold-voltage distribution profiles of memory cells can be improved as the program voltage step becomes lower. However, a too low level of the program voltage step causes the threshold voltages to be reduced in shifting width so much and the number of programming loops to increase thereby, resulting in a longer overall programming time. While a reduction of the program voltage step is effective in improving the threshold-voltage distribution profiles of memory cells, it is inevitable that this method causes a loss in operating speed. To the contrary, an increase in the program voltage step would incur a heavy loss against the threshold-voltage distribution profiles, but it accelerates a programming speed.
The problems due to the fixed verifying time are generated when the threshold voltages of memory cells are close in value to the verifying voltage Vveri. In general, sense amplifiers employed in the flash memory devices detect and amplify drain voltages discharged while the verifying voltage is being applied to wordline. If a threshold voltage of memory cell is higher than the verifying voltage Vveri, the memory cell is detected as an off-cell. However, if a threshold voltage of a memory cell is lower than the verifying voltage Vveri, the memory cell is detected as an on-cell. However, when there is only a small difference between a cell threshold voltage and the verifying voltage, (i.e., when the threshold voltage is positioned around an intermediate level between the on-cell and off-cell) a sensing time interval may need to become substantial to obtain accurate verification of the program state of a cell. If a memory cell undergoes an insufficiently long verification operation, then it may be judged as a passed cell even though its threshold voltage is at a relatively low “fail” level. As will be understood by those skilled in the art, the use of a verification operation having an insufficiently long verification time interval may cause “failed” cells to appear as “passed” cells and thereby increase a width of a threshold-voltage distribution profile.